Give and explain single phase clock system and explain drawbacks.

CMOS admits to a wide variety of clocking styles. Most of them are design based. The simplest is based on using a single-clock Ø by itself. Such system is called as single phase clock system.

Applying clock signals directly to FETs gives a simple approach for controlling data flow. In single phase clocking system we make use of single polarity transistor switches. Generally nFET is preferred over pFET. One problem with using the nFET as a clocking device is that the output is restricted to the voltage range 0 to Vmax where

Due to the threshold loss. In addition to passing a weak logic 1, the transition is quite slow.

The transmission gate passes the full voltage range with fast switching for both logic 0 and logic 1 inputs. However, a TG requires two transistors [nFET and pFET] and the associated parallel wiring increases routing problems. In modern high-speed design, single nFET tends to be used over TGs due to their simplicity. Logic 1 transmission problems are dealt with by careful design of the peripheral circuitry. If we make use of Øbar with Ø then it becomes dual phase system and sometimes it is necessary to make use of it in a single clocking system.

In a single clocking system sometimes Ø and Øbar signals simultaneously becoming high result in two types of failures:

  1. When both are 1, there is possibility of passing garbage value to the next input node.
  2. Ø= Øbar when remains high for enough long time could result race condition which destroys the state of intermediate stages.
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