Explain Dynamic CMOS logic. Compare it with static CMOS logic. What is the primary drawback of dynamic CMOS logic? Show to modifications in dynamic CMOS logic to overcome its drawback.

Static/Ratioed Circuits

Ratioed circuits are the ones which reduce the input capacitance by replacing the pMOS transistors connected to the inputs with a single resistive pull-up.

Drawback of Static Circuits:

The drawbacks of ratioed circuits include slow rising transitions, contention on the falling transitions, static power dissipation, and a non-zero VOL.

Dynamic Circuits:

A dynamic logic gate uses clocking and charge storage properties of MOSFETs to implement logic operation. The clock provides a synchronized data flow which makes the technique useful in designing sequential networks. The characterising feature of a dynamic logic gate is that the result of a calculation is valid only for a short period of time.

The clock drives a complementary pair of transistors (1 and 2); these control the operation of the circuit and provide synchronization. Logic is implemented using an nFET array between the output node and ground.

To avoid the drawback of static circuits we use dynamic circuits wherein a clocked pull-up transistor replaces the pMOS that is always ON.

Figure below compares (a) static CMOS, (b) pseudo-nMOS, and (c) dynamic inverters.


Dynamic circuit operation is divided into two modes, shown in Figures below, namely,

  1. Precharge.
  2. Evaluation.

During precharge, the clock (J) is '0,' so the clocked pMOS is ON and initializes the output Yhigh. During evaluation, the clock is '1' and the clocked pMOS turns OFF. The output may remain high or may be discharged low through the pull-down network. Dynamic circuits are the fastest commonly used circuit family because they have lower input capacitance and no contention during switching. They also have zero static power dissipation. However, they require careful clocking, consume significant dynamic power, and are sensitive to noise during evaluation.

Footed and Non-footed transistors:

In Figure 6.21(c), if the input is '1' during precharge, contention will take place because both the pMOS and nMOS transistors will be ON. When the input cannot be guaranteed to be '0' during precharge, an extra clocked evaluation transistor can be added to the bottom of the nMOS stack to avoid contention as shown in Figure. The extra transistor is sometimes called a foot Figure 6.24 shows generic footed and unfooted gates .

Monotonocity problem:

A fundamental difficulty with dynamic circuits is the monotonicity requirement. While a dynamic gate is in evaluation, the inputs must be monotonically rising. That is, the input can start LOW and remain LOW, start LOW and rise HIGH, start HIGH and remain HIGH, but not start HIGH and fall LOW. Figure shows waveforms for a footed dynamic inverter in which the input violates monotonicity .During precharge, the output is pulled HIGH. When the clock rises, the input is HIGH so the output is discharged.

LOW through the pull-down network, as you would want to have happen in an inverter. The input later falls LOW, turning off the pull-down network. However, the precharge transistor is also OFF so the output floats, staying LOW rather than rising as it Output should rise but does not would in a normal inverter. The output will remain low until the next precharge step. In summary, the inputs must be monotonically rising for the dynamic gate to compute the correct function. Unfortunately, the output of a dynamic gate begins HIGH and monotonically falls LOW during evaluation. This monotonically falling output X is not a suitable input to a second dynamic gate expecting monotonically rising signals, as shown in Figure. Dynamic gates sharing the same clock cannot be directly connected. This problem is often overcome with domino logic.

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