The ripple-carry adder's limiting factor is the time it takes to propagate the carry. The carry look-ahead adder solves this problem by calculating the carry signals in advance, based on the input signals. The result is a reduced carry propagation time.

To be able to understand how the carry look-ahead adder works, we have to manipulate the Boolean expression dealing with the full adder. The Propagate P and generate G in a full-adder, is given as:

Pi = Ai ⊕ Bi --- Carry propagate

Gi= AiBi --- Carry generate

Notice that both propagate and generate signals depend only on the input bits and thus will be valid after one gate delay.

The new expressions for the output sum and the carryout are given by:

Si= Pi⊕ Ci-1

Ci+1= Gi + Pi.Ci

These equations show that a carry signal will be generated in two cases:

1. if both bits Ai and Bi are 1
2. if either Ai or Bi is 1 and the carry-in Ci is 1.

Let's apply these equations for a 4-bit adder:

C1 = G0 + P0C0

C2 = G1 + P1

C1 = G1 + P1(G0 + P0C0) = G1 + P1G0 + P1P0C0

C3 = G2 + P2

C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0

C4 = G3 + P3

C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0

These expressions show that C2, C3 and C4 do not depend on its previous carry-in.

Therefore C4 does not need to wait for C3 to propagate. As soon as C0 is computed, C4 can reach steady state. The same is also true for C2 and C3

The general expression is

Ci+1= Gi + PiGi-1 + PiPi-1Gi-2 + ……. PiPi-1….P2P1G0 + PiPi-1 ….P1P0C0.

Carry look-ahead adder’s structure can be divided into three parts: the propagate/generate generator Fig.1, the sum generator Fig. 2 and the carry generator Fig. 3.