In ripple carry adders, the carry propagation time is the major speed limiting factor as seen in the previous lesson.

Most other arithmetic operations, e.g. multiplication and division are implemented using several add/subtract steps. Thus, improving the speed of addition will improve the speed of all other arithmetic operations.

Disadvantages:

The disadvantage of the ripple-carry adder is that it can get very slow when one needs to add many bits. For instance, for a 32-bit adder, the delay would be about 63 ns if one assumes a gate delay of 1 ns. That would imply that the maximum frequency one can operate using the ripple carry adder would be only 16 MHz! For fast applications, a better design is required. The carry-look-ahead adder solves this problem by calculating the carry signals in advance, based on the input signals. It is based on the fact that a carry signal will be generated in two cases:

(1) When both bits Ai and Bi are 1, or

(2) When one of the two bits is 1 and the carry-in (carry of the previous stage) is 1.

To understand the carry propagation problem, let’s consider the case of adding two n-bit numbers A and B.

Summation of n-bit numbers:

The Figure shows the full adder circuit used to add the operand bits in the  column; namely  and the carry bit coming from the previous column $(C_i)$ .

Bit full adder circuit: