For the digital system shown above, when A=1 value at input is gven to the combinational logic CL1. After computational delay of combinational logic the value is available at input stage 2.

Hence, before the stage 2 pulse Abar arrives, computation of data must be completed for stage 1.

Net delay in stage 1 = tpd,inv + tpd,CL

Considering the skew time or wiring delay we get

(T/2)min= tpd,inv + tpd,CL

And (T/2) >= tpd,inv + tpd,CL

fmax = (1/Tmin)=1/2(tpd,inv + tpd,CL)....(i)

Now, when a transistor (NMOS here) is off, leakage current flows through it and the data at a terminal may get switched and hence lost.

Therefore refresh pulse must be applied before hold time of circuit.

[Data will be altered after hold time]

Therefore (T/2) > th

(T/2)max = th

fmin = (1/Tmax)= (1/2th)....(ii)

Equation (i) and (ii) gives minimum and maximum frequency of a digital syste.