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written 2.9 years ago by |

It is necessary for a chip designer to limit the power dissipation under given constraints. Hence low power design consideration comes into picture.

The instantaneous total power dissipation is the sum

There are three main sources of power dissipation in a digital CMOS circuit.

*DC Leakage*

DC power PDC that is due to direct conduction paths from VDD to ground when inputs are stable. Leakage currents are the cause of this component in standard static CMOS logic circuits.

Now,

where IDDQ is the quiescent leakage current that flows when the inputs are not changing. The value of the leakage current for a transistor is process-dependent. The total IDDQ for the chip increases with the number of transistors and also depends upon the circuit design technique.

*Switching power (PSW*) that is dissipated when an input change causes the power supply to have a direct current flow path to ground through the transistors. This occurs during the transition portion of a voltage transfer curve (VTC).

*Switching Power (Psw*) is a consequence of a gate input signal transition causing a direct current flow path from VDD to ground and is the origin of SSN. It occurs every time the output voltage undergoes a voltage transition, and originates with the circuit design. It is given as

where Isw is the average DC current flow. The contribution from an isolated gate varies with the transistor aspect ratios, since (W/L) determines the current flow level through a FET. The actual depends upon the shape of the input waveform, making it difficult to calculate using closed-form equations.

Dyanmic switching power(Pdyn) due to charging and discharging capacitive nodes. This is estimated from the general formula

where,

C is the capacitance in farads,

α is the activity co-efficient,

V is the voltage swing, and

f is the signal frequency.

Pdyn increases proportionately with the signal switching frequency f so that it grows with the speed of the circuit. One approach to decreasing the magnitude of this term is to reduce the power supply voltage VDD since it is the maximum DC value for V. This also reduces the values of the other contributions. Processor core voltages are currently below 2 V, and the push is on for even lower operating voltages. A reduced power supply voltage is also advantageous in battery-operated units.