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Provide description of exceptions in ARM7TDMI (interrupts)
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The ARM processor supports five types of exceptions and privileged processing mode for each type.

The types of exception are :

  1. Normal interrupt.
  2. Fast interrupt.
  3. Memory aborts that are used to implement memory protection or virtual memory.
  4. Attempt to execute an undefined instruction.
  5. Software interrupt instructions that are used to make a call to the operating system.

Whenever an exception occurs, the standard registers are replaced with registers that are specific to the exception mode.

The exception modes have replacement banked registers for R13 and R15.

For fast interrupt processing there are more registers as the processing has to be done fast.

R14 contains the return address for exception processing. Once the exception is processed R14 returns to the address that caused the exception.

The system mode uses the user mode registers in order to run the tasks that require privilege access to memory and/or coprocessors without limitations.

R13 provides each exception handler an individual separate stack pointer.

Exception process

  • When an exception occurs, the ARM processor stops the execution of current instruction and continues execution from one of the fixed addresses referred as exception vector in memory. For each exception there is a separate vector location.

  • Processor copies the CPSR register to the SPSR. Then appropriate CPSR bits are set. If the core implements ARM architecture 4T and is in the Thumb state, then the ARM state is entered.

  • It stores the return address in R14.

  • Maps the appropriate banked registers.

  • To return from the exception handler the CPSR is restored from the SPSR and PC from R14.

Exceptions are generated by internal and external sources that cause the processor to handle events like externally generated interrupt or attempt to execute an undefined instruction. At a time more than one exception can take place. The table below consists the types of exceptions and the processor mode used to process that exception.

Exception type Mode Normal address High vector address
Reset Supervisor 0x00000000 0xFFFF0000
--- --- --- ---
Undefined instructions Undefined 0x00000004 0xFFFF0004
Software interrupt (SWI) Supervisor 0x00000008 0xFFFF0008
Prefetch Abort (instruction fetch memory abort) Abort 0x0000000C 0xFFFF000C
Data Abort (data access memory abort) Abort 0x00000010 0xFFFF0010
IRQ (interrupt) IRQ 0x00000018 0xFFFF0018
FIQ (fast interrupt) FIQ 0x0000001C 0xFFFF001C

Reset

When Reset pin is activated, the current execution is stopped by the processor. After reset the processor begins execution at an address 0x00000000 or 0xFFFF0000 is the supervisor mode with interrupts disabled.

Undefined instructions

Whenever an attempt is made to execute an undefined instruction, an undefined instruction exception occurs. If a coprocessor instruction is executed, the processor waits for any external coprocessor to acknowledge that it can execute the instruction. In case no external processor acknowledges, an undefined instruction exception occurs.

Software interrupt

Whenever a software interrupt instruction is executed a software interrupt exception is caused. The processor enters the supervisor mode in order to request a particular supervisor function.

Prefetch abort vector

This exception is generated if the processor tries to execute an invalid instruction. If the instruction is not executed then no prefetch abort exception occurs.

This exception can also be generated as a result of executing a breakpoint instruction in ARM architecture version 5 and above.

Data abort

A memory abort is signalled by the memory system. Activating an abort in response to data access (i.e. load or store) marks the data as invalid.

Interrupt request (IRQ)

This exception is generated by asserting the IRQ input on the processor. When the I bit in CPSR is set, this interrupt is disabled. It has a lower priority than the FIQ. If the I bit in CPSR is clear then the processor checks for an IRQ at instruction boundaries.

Fast interrupt request (FIQ)

If the FIQ input is asserted, an FIQ exception is generated. FIQ supports data transfer or channel process and has sufficient private registers to remove the need for register saving in such applications minimizing the overhead of context switching. Fast interrupts are disabled if the F bit in CPSR is set. If the bit is clear then the processor checks for an FIQ at instruction boundaries.

High vectors

Some of the ARM implementations allow the exception vector locations to be shifted from their normal address 0x00000000-0x0000001C to address 0xFFFF0000-0xFFFF001C. These locations are called as high vectors.

Exception priorities

Table shows the exception priorities

Priority Exception
Highest 1 Reset
2 Data Abort
3 FIQ
4 IRQ
5 Prefetch Abort
Lowest  6 Undefined instruction, SWI

The priority of a data abort exception is higher than FIQ. The priority of SWI and undefined instruction is same. But, both of them cannot take place at the same time.

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