written 2.9 years ago by |

*The various sources of clock for the MSP 430 processor are:*

- LFXT1CLK: It is a low / high frequency oscillator which can be used either with low frequencies like 32768Hz to high frequencies upto 8MHz.
- XT2CLK: It is a high frequency oscillator and can be used with high frequency crystals of upto 8MHz.
- DCOCLK: It is an internal oscillator controlled digitally with the characteristics as an RC oscillator.

*The various clocks available are:*

- ACLK (Auxiliary Clock): It is the LFXT1CLK source clock with a prescaler of 1,2,4 or 8. It is used by peripherals.
- MCLK (Master Clock): It has a selectable clock source from either LFXT1CLK, XT2CLK or DCOCLK. It also has a prescaler of 1,2,4 or 8. It is used by the main processin unit.
- SMCLK (Sub-main clock): It also has a selectable clock source from either LFXT1CLK, XT2CLK or DCOCLK. It also has a prescaler of 1,2,4 or 8. It is used by the peripheral modules.

*The various registers required to control the function of the clock module are as listed below:*

*1.BCSCTL1*

| XT2Off | XTS | DIVA.1 | DIVA.0 | XT5V | RSEL.2 | RSEL.1 | RSEL.0 | | --- | --- | --- | --- | --- | --- | --- | --- | This is the basic clock system control 1 register. The various bits have following significance:

*RESL.2, RSEL.1, RSEL.0:* These bits are used to select the DCO nominal frequency.

*XT5V* should always be reset

*DIVA.1 and DIVA.0*: These bits are used to decide the prescaler value or the dividing factor for the frequency for ACLK. The factors are 1, 2, 4 and 8 for the values of DIVA.1 and DIVA.0 as 00, 01, 10 and 11.

*XTS*: This bit is used to indicate whether the LFXT1 is supposed to work on low frequency or high frequency.

*XT2Off*: This bit is used to switch 'ON' or 'OFF' the XT2CLK clock source.

*2.BCSCTL2*

| SELM.1 | SELM.0 | DIVM.1 | DIVM.0 | SELS | DIVS.1 | DIVS.0 | DCOR | | --- | --- | --- | --- | --- | --- | --- | --- | This is the basic clock system control 2 register. The various bits have following significance:

*DCOR*: It is used to decide the internal pull up resistor to be activated or deactivated for the clock source.

*DIVS.1 and DIVS.0*: These bits are used to decide the prescaler value or the dividing factor for the frequency for SMCLK. The factors are 1, 2, 4 and 8 for the values of DIVS.1 and DIVS.0 as 00, 01, 10 and 11.

*SELS (Select source for SMCLK)*: It is used to decide the source for the SMCLK to be DCOCLK or XT2CLK.

*DIVM.1 and DIVM.0:* These bits are used to decide the prescaler value or the dividing factor for the frequency for MCLK. The factors are 1, 2, 4 and 8 for the values of DIVM.1 and DIVM.0 as 00, 01, 10 and 11.

*SELM.1 and SELM.0*: These bits are used to decide the source for MCLK to be DCOCLK, XT2CLK or LFXT1CLK.

*3.DCOCTL*

| DCO.2 | DCO.1 | DCO.0 | MOD.4 | MOD.3 | MOD.2 | MOD.1 | MOD.0 | | --- | --- | --- | --- | --- | --- | --- | --- | This is the DCO control register. The various bits have following significance:

*DCO.2, DCO.1, DCO.0:* These bits are used to select one of the eight discrete DCO frequencies is selected.

*MOD.4, MOD.3, MOD.2, MOD.1, MOD.0*: These bits are used to define how often frequency within the period of 32 DCOCLK cycles are used. The DCO frequency will be used for 32 - MOD frequency, where MOD is the value given by the 5 bits MOD.4 to MOD.0