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Explain 4-bit successive approximation type ADC.
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1) Successive approximation is one of the most widely and popularly used ADC technique. It uses an efficient “code search” strategy to complete n-bit conversion in just n-clock periods. Thus it takes much shorter conversion time than counter type ADC.

2) Figure 1 shows the block diagram of successive approximation DAC. An four bit converter would require eight clock pulses to obtain a digital output.

3) To start conversion “SOC” input is made 1. As soon as “SOC” input is 1, SAR will set MSB to 1 and all other bits to 0 so that trial code output of SAR is D1,D2,D3,D4 = 1000.

4) The output of SAR is then applied to DAC. The corresponding output DAC $V_D$ is applied to comparator.

5) If $V_D$< $Va$ i.e trial code is less than the correct digital representation then output goes high which is applied to SAR.

6) In response to high comparator output, MSB D1 is maintained at 1 and the next bit D2 is made 1. The trial code at the SAR output now becomes 1100. The corresponding DAC output is compared with $Va$ and the process continues.

7) However for the first trial code, $V_D$>$Va$, then the comparator output will go low i.e. 0. The SAR will respond to it by reseting its MSB bits D1 to 0 and next bit D2=1 so that the new trial code is 0100.

8) The procedure is repeated for all the subsequent bit one at a time, until all bit position are tested. When all the bit positions are tested, end of conversion (EOC) output goes high to indicate conversion is over.

9) The complete conversion sequence for 4-bit successive approximation ADC is shown in Figure 2. It can be seen that the DAC output voltage becomes successively closer to the actual analog input voltage. It requires n pulses equivalent to n bits to establish the accurate output regardless of the value of the analog input.