Draw the circuit diagram of JK FF using NAND gates. Derive its characteristic equation and excitation table.

What is race around condition in JK FF and how it is avoided?

1 Answer
  • JK flip flop is a memory element similar to the SR flip flop. The sequential operation of the JK flip flop is exactly the same as for SR flip-flop with the same “Set” and “Reset” inputs. The difference is that the “JK flip flop” has no invalid or forbidden input states of the SR Latch even when S and R are both at logic “1”. In fact, the flip flop toggles when the inputs are both 1.

  • The circuit diagram and the truth table of a JK flip flop using NAND gates is shown below.

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  • The characteristic equation of JK flip flop is shown below:

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  • To find the excitation table, we need to consider the present state and next state outputs. The excitation table of JK flip flop is shown below.

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  • Race Around condition :

The Race Around condition occurs when J=K=1 i.e. when the latch is in toggle mode. The following waveform shows various modes when a rectangular wave is applied to Clock/E input. Consider the time interval $t_2-t_3$. At instant $t_2$, J=K=1 and E=1. Hence the latch is in toggle mode and output Q=0 and Q'=1. These changed outputs get applied to inputs of NAND 3 and 4. But J and K are still 1, hence after a time interval of propagation delay, Q and Q' outputs will again toggle and become Q=1, Q'=0. These changed outputs get applied to the NAND gates again and the toggling continues indefinitely until J=K=E=1, as shown in the waveforms. This is known as Race Around.

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  • Avoiding Race Condition:

Race around condition can be avoided by using

  1. Using edge triggered JK Flip flop

  2. Using Master-Slave JK Flip flop.

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