Question: Design MOD 6 asynchronous counter and explain glitch problem
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Mumbai University > ELECTRO > Sem 3 > Digital Circuits and Designs

Marks: 10M

Year: May 2014

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modified 3.2 years ago  • written 3.2 years ago by gravatar for Pooja Joshi Pooja Joshi740
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  • MOD 6 asynchronous counter will require 3 flip flops and will count from 000 to 101. Rest of the states are invalid. To design the combinational circuit of valid states, following truth table and K-map is drawn:

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  • From the above truth table, we draw the K-maps and get the expression for the MOD 6 asynchronous counter.

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  • Thus reset logic is OR of complemented forms of QC and QB. This will be given to the reset inputs of the counter so that as soon as count 110 reaches, the counter will reset. Thus the counter will count from 000 to 101. The implementation of the designed MOD 6 asynchronous counter is shown below:

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  • Glitch: glitch is a short duration pulse or spike that appears in the outputs of a ripple counter with number<2n. Consider the waveform of a MOD-3 ripple counter shown below. But in practice, at the third falling clock edge, QB and QA become 11 causing a pulse. Hence output of reset logic goes low but after a short duration of time. Here 11 is an unwanted state. In the output waveform of QA, this short pulse is called a 'Glitch'.

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written 3.2 years ago by gravatar for Pooja Joshi Pooja Joshi740
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