Question: Design MOD 10 asynchronous counter
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Mumbai University > ELECTRO > Sem 3 > Digital Circuits and Designs

Marks: 10M

Year: Dec2014

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modified 3.2 years ago  • written 3.2 years ago by gravatar for Pooja Joshi Pooja Joshi740
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  • MOD 10 asynchronous counter counts from 0000 to 1001. Rest of the states are invalid. To design the combinational circuit of valid states, following truth table and K-map is drawn:

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  • From the above truth table, we draw the K-maps and get the expression for the MOD 10 asynchronous counter.

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  • Thus the above K-map shows the expression for Y which is the reset logic. This will be given to the reset inputs of the counter so that as soon as count 1010 reaches, the counter will reset. Thus the counter will count from 0000 to 1001. The implementation of the designed MOD 10 asynchronous counter is shown below:

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written 3.2 years ago by gravatar for Pooja Joshi Pooja Joshi740
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