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Solution:
EPROM Technology:
In certain programmable logic devices, the programmable links are similar to the memory cells in EPROMs (electrically programmable read-only memories).
This type of PLD is programmed using a special tool known as a device programmer. The device is inserted into the programmer, which is connected to a computer running the programming software.
Most EPROM-based PLDs are one-time programmable (OTP). However, those with windowed packages can be erased with UV (ultraviolet) light and reprogrammed using a standard PLD programming fixture.
EPROM process technology uses a special type of MOS transistor, known as a floating-gate transistor, as the programmable link.
The floating-gate device utilizes a process called Fowler-Nordheim tunneling to place electrons in the floating-gate structure.
In a programmable AND array, the floating-gate transistor acts as a switch to connect the row line to either a HIGH or a LOW, depending on the input variable.
For input variables that are not used, the transistor is programmed to be permanently off (open).
Figure shows one AND gate in a simple array. Variable A controls the state of the transistor in the first column, and variable B controls the transistor in the third column.
When a transistor is off, like an open switch, the input line to the AND gate is at +V (HIGH). When a transistor is on, like a closed switch, the input line is connected to ground (LOW).
When variable Aor B is 0 (LOW), the transistor is on, keeping the input line to the AND gate LOW. When A or B is 1 (HIGH), the transistor is off, keeping the input line to the AND gate HIGH.
SRAM Technology:
SRAM technology is different from the other process technologies discussed because it is a volatile technology.
Many FPGAs and some CPLDs use a process technology similar to that used in SRAMs (static random-access memories). The basic concept of SRAM-based programmable logic arrays is illustrated in Figure (a).
A SRAM-type memory cell is used to turn a transistor on or off to connect or disconnect rows and columns.
For example, when the memory cell contains a 1 (green), the transistor is on and connects the associated row and column lines, as shown in part (b).
When the memory cell contains a 0 (blue), the transistor is off so there is no connection between the lines, as shown in part (c).
This means that a SRAM cell does not retain data when power is turned off. The programming data must be loaded into a memory; and when power is turned on, the data from the memory reprograms the SRAM-based PLD.
The fuse, antifuse, EPROM, EEPROM, and flash process technologies are nonvolatile, so they retain their programming when the power is off.
A fuse is permanently open, an antifuse is permanently closed, and floating-gate transistors used in EPROM and EEPROM based arrays can retain their on or off state indefinitely.