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Discuss XC 9500 CPLD family architecture with neat block diagram. Describe main features.

Mumbai University > ELECTRO > Sem 3 > Digital Circuits and Designs

Marks: 10M

Year: Dec 2013 , May 2015

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  • The Xilinx XC 9500 is a family of Complex Progammable Logic Devices (CPLDs). The internal PLDs in Xilinx are called as function blocks (FBs).

  • Each internal PLD has 36 inputs and 18 macrocells and outputs. Hence it is called as a “36V18”.

  • The devices in this family are named according to the number of macrocells it contains. The smallest CPLD has 2 FBs and 36 macrocells whereas the largest contains 16FBs and 288 macrocells. The other important feature is that the ICs from this family are available in different packages.

  • The main features of this family of CPLD are:

    • High-performance

    • 5 ns pin-to-pin logic delays on all pins

    • fCNT to 125 MHz

    • Large density range: 36 to 288 macrocells with 800 to6,400 usable gates

    • 5V in-system programmable

    • Endurance of 10,000 program/erase cycles

    • Program/erase over full commercial voltage and temperature range

    • Enhanced pin-locking architecture

    • Flexible 36V18 Function Block

    • 90 product terms drive any or all of 18 macrocells within Function Block

    • Global and product term clocks, output enables, set and reset signals

    • Extensive IEEE Std 1149.1 boundary-scan (JTAG) support

    • Programmable power reduction mode in each macrocell

    • Slew rate control on individual outputs - User programmable ground pin capability

    • Extended pattern security features for design protection

    • High-drive 24 mA outputs

    • 3.3V or 5V I/O capability

  • The figure below shows the block diagram of the internal architecture of the XC 9500 family CPLD.

  • The external I/O pins can be used as input, output or bi-directional pins according to device programming. The pins marked I/O/GCK, I/O/GSR and I/O/GTS are special purpose pins. Any of these pins can b e used as global clocks (GCK). The same pin can be used as an asynchronous preset or clear. Two or four pins can be used as global three state controls (GTS).

  • The figure below shows only four FBs but in XC 9500 architecture it is possible to include upto 16 FBs. Each FB will receive 36 signals from the switch matrix, the macrocell outputs from each of the FB and the external inputs from the I/O pins are applied to the switching matrix. Each FB has 18 outputs which run “under” the switch matrix and connect to the I/O blocks. These signals are only the output enable signals for the I/O block output drivers.

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