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Write a VHDL code for 8:1 Multiplexer with active low enable input
written 9.4 years ago by gravatar for teamques10 teamques10 ★ 70k modified 3.8 years ago by gravatar for pedsangini276 pedsangini276 • 4.8k

Mumbai University > ELECTRO > Sem 3 > Digital Circuits and Designs

Marks: 10M

Year: May 2014
digital circuits and design
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written 9.4 years ago by gravatar for teamques10 teamques10 ★ 70k •   modified 9.4 years ago

library IEEE;

use IEEE.std_logic_1164.all;

entity mux is

port (sel : in std_logic_vector(2 downto 0);

A,B,C,D,E,F,G,H, enable: in std_logic;

Y : out std_logic);

end mux;

architecture mux8 of mux is

begin

if (enable==0)

then

begin

process (sel, A,B,C,D,E,F,G,H)

begin

case sel is

when “000” => Y <=A;

when “001” => Y …

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