Write a VHDL code for full adder

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written 9.4 years ago by

teamques10 ★ 70k

modified 3.8 years ago by

pedsangini276 • 4.8k

Mumbai University > ELECTRO > Sem 3 > Digital Circuits and Designs

Marks: 10M

Year: Dec 2014

digital circuits and design

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written 9.4 years ago by

teamques10 ★ 70k

library IEEE;

use IEEE.std_logic_1164.all;

entity fulladder is

port (a : in std_logic

b : in std_logic;

cin : in std_logic;

sum : out std_logic;

cout :out std_logic);

end adder;

architecture FA of fulladder is

begin

sum <= (a xor b) xor cin;

cout <= (a and b) or (cin and …

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