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Write a VHDL code for full adder
written 7.8 years ago by | modified 2.2 years ago by |
Mumbai University > ELECTRO > Sem 3 > Digital Circuits and Designs
Marks: 10M
Year: Dec 2014
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written 7.8 years ago by | modified 2.2 years ago by |
Mumbai University > ELECTRO > Sem 3 > Digital Circuits and Designs
Marks: 10M
Year: Dec 2014
written 7.8 years ago by |
library IEEE;
use IEEE.std_logic_1164.all;
entity fulladder is
port (a : in std_logic
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
cout :out std_logic);
end adder;
architecture FA of fulladder is
begin
sum <= (a xor b) xor cin;
cout <= (a and b) or (cin and a) or (cin and b);
end FA;