Write short note on: Automatic Test Pattern Generation (ATGP)

Mumbai University > ELECTRO > Sem 3 > Digital Circuits and Designs

Marks: 7M

Year: May 2015

1 Answer
  • ATPG stands for automatic test pattern generation. ATPG is an electronic design automation method/technology which involves generation of input patterns or sequence which when applied to a digital circuit can ascertain the presence or absence of faults at some locations in a circuit.

    • There are several ways of ATPG such as (i) fault simulation and (ii) sensitization–propagation –justification. These techniques are based on Boolean logic manipulations and are most widely used. The generated patterns are used to test semiconductor devices after manufacture, and in some cases to assist with determining the cause of failure.

    • A defect is an error caused in a device during the manufacturing process. A fault model is a mathematical description of how a defect alters design behaviour.

    • The logic values observed at the device's primary outputs, while applying a test pattern to some device under test (DUT), are called the output of that test pattern. The output of a test pattern, when testing a fault-free device that works exactly as designed, is called the expected output of that test pattern.

    • The combinational ATPG method allows testing the individual nodes (or flip-flops) of the logic circuit without being concerned with the operation of the overall circuit. During test, a so-called scan-mode is enabled forcing all flip-flops (FFs) to be connected in a simplified fashion, effectively bypassing their interconnections as intended during normal operation. This allows using a relatively simple vector matrix to quickly test all the comprising FFs, as well as to trace failures to specific FFs.

    • The effectiveness of ATPG is measured by the amount of modelled defects, or fault models, that are detected and the number of generated patterns.

    • ATPG efficiency is another important consideration. It is influenced by the fault model under consideration, the type of circuit under test (full scan, synchronous sequential, or asynchronous sequential), the level of abstraction used to represent the circuit under test (gate, register-transfer, switch), and the required test quality

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