Mumbai University > COMPS > Sem 3 > Digital Logic Design and Analysis

Marks: 10 M

Year: June 2014

1) Excitation Table:

2) K-map:

*3) Logic Diagram: *

4) Lock out condition:

• In the above counter the logic states 001, 010, 100 and 111 are not used. If by chance, the counter happens to find itself in any one of the unused states, its next state would not be known. It may just be possible that the counter might go from one unused state to another and never arrive at a used state. A counter whose unused states have this feature is said to suffer from LOCK OUT.

To avoid lock out and make sure that at the starting point the counter is in its initial state or it comes to its initial state within few clock cycles, external logic circuitry is to be provided and so we design the counter assuming the next state to be the initial state, from each unused states.