Mumbai University > COMPS > Sem 3 > Digital Logic Design and Analysis

Marks: 10 M

Year: June 2014

1) Schematic diagram:

2) Truth Table:

3) Working:

• A master-slave JK flip flop is a cascade of 2 SR flip flops, with feedback from the outputs of the second to the inputs of the first as shown in the figure above.
• The positive clock pulses are applied to the first flip flop and the clock pulses are inverted before these are applied to the second flip flop.
• When CK=1 the first flip flop is enabled and outputs QM and QM respond to the inputs J and K. At this time, the second flip flop is inhibited because its clock is LOW (CK=0).
• When CK goes LOW, the first flip flop is inhibited and second flip flop is enabled, because now its clock is HIGH(CK = 1). Therefore the outputs Q and Q follow the outputs QM and QM, respectively.
• Since the second flip flop simply follows the first one, it is referred to as slave and the first one as master, Hence this - In this circuit, the inputs to the gates G3M and G4M do not change during the clock pulse, therefore the race-around condition does not exist. The state of the master-slave flip flop changes at the negative transition of the clock pulse.