**1 Answer**

written 17 months ago by | • modified 17 months ago |

**Solution:**

when the sum of two fixed point fraction d numbers is greater than the dynamic range of the $(\mathrm{B}+1)$ bit number in the given format, overflow occurs.

This is because when a two's complement representation overflows, it goes from a significant positive to a large negative number.

This characteristic assumes that the number is fractioned in the range $-1 \leq x \leq 1$.

Thus the limit cycle can occur due to overflow in addition

The filter output oscillates between the maximum amplitude limits.

Such limit cycles are referred to as

overflow limit cycles or overflow oscillations.

The following techniques can be used to prevent overflow limit cycles.

**(1) Saturation to Avoid overflow:**

We can force the output to saturate if an overflow occurs.

In other words; when the result of adding two positive numbers is greater than the maximum positive value that can be represented, the processor clips the result to that maximum positive value.

When the result of adding two negative numbers is smaller than -1, the processor clips the result to -1.

**(2) Scaling to Prevent Overflow:**

In order to prevent overflow, the input signal to the adder must be scaled down such that the adder output remains within the specified dynamic range.