Mumbai University > COMPS > Sem 3 > Digital Logic Design and Analysis

Marks: 10 M

Year: June 2014

1) FPGA:

• FPGA stands for Field Programmable Gate Array and has been developed to increase the effective size and to add more functionality in a single programmable device. The FPGAs do not contain AND, OR planes, instead they provide logic blocks for implementation of the required digital functions.
• An FPGA is composed of number of relatively independent configurable logic blocks (CLBs), configurable I/O blocks, and programmable interconnection paths known as routing channels.
• All the resources of the device are uncommitted and that these must be selected, configured and interconnected by a user to form a logic circuit for this application.
• The basic architecture consists of an array of configurable logic blocks. The logic blocks are surrounded by configurable I.O blocks. The I/O blocks can be individually configured as input, output or bidirectional.
• A logic block consists of a number of logic modules. The logic modules are basic elements in an FPGA. The logic modules within a CLB are connected through local programmable interconnects.
• A logic module consists of an Look up table, D-Flip Flop and a multiplexer. An Look-up table consists of a programmable memory and is used to generate a logic function in SOP form.

2) CPLD:

• CPLD stands for Complex Programmable Logic Devices and are designed to increase the number of inputs and outputs that are available in a single SPLD chip.
• CPLD consists of number of PAL-like blocks, I/O blocks and set of interconnection wires. The PAL-like blocks are connected to a set of interconnection wires and each block is also connected to an I/O block to which a number of chip’s input and output pins are attached.
• A PAL-like block usually consists of about 16 macrocells. Each macrocell consists of an AND-OR configuration, an EX-OR gate, a FLIP FLOP, and a multiplexer and a tri state buffer.
• Each AND-OR configuration usually consists of 5-20 AND gates and an OR gate input. The tri-state buffer acts as a switch which enables the chip’s pin to be used either as an output or as an input.
• In case the chip’s pin is used as an input pin, an external source can drive a signal pin to the pin which can be connected to other macrocells using the interconnection wiring. When used as an input pin, the macrocellbecomes redundant and it is wasted.