A typical instruction cycle can be split into many sub cycles like Fetch instruction, Decode instruction, Execute and Store. The instruction cycle and the corresponding sub cycles are performed for each instruction. These sub cycles for different instructions can thus be interleaved or in other words these sub cycles of many instructions can be carried out simultaneously, resulting in reduced overall execution time. This is called instruction pipelining.
The more are the stages in the pipeline, the more the throughput is of the CPU.
If the instruction processing is split into six phases, the pipelined CPU will have six different stages for the execution of the sub phases.
The six stages are as follows:
- Fetch instruction (FI):
- Decode instruction ((DI):
- Calculate operand (CO):
- Fetch operands (FO):
- Execute Instruction (EI):
Write operand (WO):
Fetch instruction: Instructions are fetched from the memory into a temporary buffer before it gets executed.
Decode instruction: The instruction is decoded by the CPU so that the necessary op codes and operands can be determined.
Calculate operand: Based on the addressing scheme used, either operands are directly provided in the instruction or the effective address has to be calculated.
Fetch Operand: Once the address is calculated, the operands need to be fetched from the address that was calculated. This is done in this phase.
Execute Instruction: The instruction can now be executed.
Write operand: Once the instruction is executed, the result from the execution needs to be stored or written back in the memory.
- The timing diagram of a six stage instruction pipeline is shown in Figure 6:
6. Assuming that the sub cycles of the instruction cycle take exactly the same time to complete i.e. one clock cycle in this case.
7. In case the time required by each of the sub phase is not same appropriate delays need to be introduced. From this timing diagram it is clear that the total execution time of 3 instructions in this 6 stages pipeline is 8-time units. The first instruction gets completed after 6 time unit, and thereafter in each time unit it completes one instruction. Without pipeline, the total time required to complete 3 instructions would have been 18 (6 3) time units. Therefore, there is a speed up in pipeline processing and the speed up is related to the number of stages.