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chewelameck

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Last seen:
7 years, 11 months ago
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7 years, 11 months ago

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  • 34
    Questions
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  • 19
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Top contributions by chewelameck

3
votes
1
answer
41k
views
1
answer
Design a VHDL Code for 4 bit full adder.
digital system design updated 3.9 years ago by krithikkm200 • 10
1
vote
1
answer
39k
views
1
answer
Write Short note on ROM & RAM architecture.
digital system design updated 3.9 years ago by krithikkm200 • 10
2
votes
1
answer
31k
views
1
answer
Compare Between Concurrent & Sequential Statements
digital system design updated 3.9 years ago by krithikkm200 • 10
1
vote
1
answer
20k
views
1
answer
Write a Short Note on Modeling Styles of VHDL.
digital system design updated 3.6 years ago by teamques10 ★ 70k
0
votes
1
answer
17k
views
1
answer
Design a VHDL Code for T Flip-Flop.
digital system design updated 3.9 years ago by krithikkm200 • 10
0
votes
1
answer
14k
views
1
answer
Design a mealy sequence detector to detect 1010 using D flip-flops & Logic Gates.
digital system design updated 3.9 years ago by krithikkm200 • 10
0
votes
1
answer
14k
views
1
answer
Design a VHDL Code for 4 Bit Ripple Carry Adder.
digital system design updated 3.9 years ago by krithikkm200 • 10
0
votes
1
answer
14k
views
1
answer
Design a VHDL Code for Multiplexer & Demultiplexer.
digital system design updated 3.9 years ago by krithikkm200 • 10
0
votes
1
answer
12k
views
1
answer
Write Short note on PLA, PAL architecture.
digital system design updated 3.9 years ago by krithikkm200 • 10
0
votes
1
answer
12k
views
1
answer
Write a VHDL Code for JK Flip-Flop.
digital system design updated 3.9 years ago by phenjoisilab • 0
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