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snehalshinde

gravatar for snehalshinde
Reputation:
Level 3
Status:
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Last seen:
7 years, 10 months ago
Joined:
7 years, 10 months ago

Profile Strength:
20%
  • 34
    Questions
  • 0
    Answers
  • 19
    Awards
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Top contributions by snehalshinde

3
votes
1
answer
41k
views
1
answer
Design a VHDL Code for 4 bit full adder.
digital system design updated 3.9 years ago by pedsangini276 • 4.8k
1
vote
1
answer
39k
views
1
answer
Write Short note on ROM & RAM architecture.
digital system design updated 3.9 years ago by pedsangini276 • 4.8k
2
votes
1
answer
31k
views
1
answer
Compare Between Concurrent & Sequential Statements
digital system design updated 3.9 years ago by pedsangini276 • 4.8k
1
vote
1
answer
20k
views
1
answer
Write a Short Note on Modeling Styles of VHDL.
digital system design updated 3.6 years ago by teamques10 ★ 70k
0
votes
1
answer
17k
views
1
answer
Design a VHDL Code for T Flip-Flop.
digital system design updated 3.9 years ago by pedsangini276 • 4.8k
0
votes
1
answer
14k
views
1
answer
Design a VHDL Code for 4 Bit Ripple Carry Adder.
digital system design updated 3.9 years ago by pedsangini276 • 4.8k
0
votes
1
answer
14k
views
1
answer
Design a mealy sequence detector to detect 1010 using D flip-flops & Logic Gates.
digital system design updated 3.9 years ago by pedsangini276 • 4.8k
0
votes
1
answer
14k
views
1
answer
Design a VHDL Code for Multiplexer & Demultiplexer.
digital system design updated 3.9 years ago by pedsangini276 • 4.8k
0
votes
1
answer
12k
views
1
answer
Write Short note on PLA, PAL architecture.
digital system design updated 3.9 years ago by pedsangini276 • 4.8k
0
votes
1
answer
12k
views
1
answer
Write a VHDL Code for JK Flip-Flop.
digital system design updated 3.9 years ago by sagarkolekar ★ 11k
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Latest awards to snehalshinde


created a question with more than 1,000 views

created a question with more than 5,000 views