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A suspension cable of 130m horizontal span is supported at the same level. It is subjected to a UDL of 28.5KN per horizontal meter. If the maximum tension in the cable is limited to 5000KN.
structural analysis updated 4.3 years ago by teamques10 ★ 70k
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A suspension cable having supports at the same level, has a span of 30m and a maximum dip of 3m. The cable is loaded with U.D.L of 10KN/m through out its length. Find the maximum and minimum tension.
structural analysis updated 4.3 years ago by teamques10 ★ 70k
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A suspension cable is supported at 2 points 2.5m apart. The left support us 2.5m above the right support. The cable is loaded with a uniformly distributed load of 10KN/m throughout the span.
structural analysis updated 4.3 years ago by teamques10 ★ 70k
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Calculate the max B.M & S.F. at 8m from left support
structural analysis updated 4.3 years ago by teamques10 ★ 70k
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Find the volume bounded by the cylinder $x^2+y^2=4$ and the planes $y+z=a$ and $z=0\cdot(H)$
engineering mathematics updated 4.3 years ago by teamques10 ★ 70k
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Find the volume in the first octant bounded by the cylinder $x^2 + y^2 = 2$ and the planes $z = x + y,\, y = x,\, z = 0$ and $x = 0(H)$
engineering mathematics updated 4.3 years ago by teamques10 ★ 70k
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Using triple integration find the volume of the ellipsoid $\frac{x^2}{a^2}+\frac{y^2}{b^2}+\frac{z^2}{c^2}=1$ .
engineering mathematics updated 4.3 years ago by teamques10 ★ 70k
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A beam of rectangular cross section $80\times120$ mm is subjected to a uniformly distributed load of 10 kN/m. The plane of loading makes an angle of $30^\circ$ with respect to y-axis.
structural analysis updated 4.3 years ago by teamques10 ★ 70k
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Explain Cascode stage, ssm, $r_o$
cmos vlsi design updated 4.3 years ago by teamques10 ★ 70k
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Explain i/p referred noise voltage of CS
cmos vlsi design updated 4.3 years ago by teamques10 ★ 70k
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Calculate $A_v$ from below circuit.
cmos vlsi design updated 4.3 years ago by teamques10 ★ 70k
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For a n-MOS draw (a) basic small signal Model (b) small signal model considering channel length modulation (c) considering body effect
cmos vlsi design updated 4.3 years ago by teamques10 ★ 70k
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Describe 2 - stage operational amplifier
cmos vlsi design updated 4.3 years ago by teamques10 ★ 70k
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Explain Gain -boosted Operational Amplifier
cmos vlsi design updated 4.3 years ago by teamques10 ★ 70k
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Explain Gain & phase margin condition while designing operational amplfiers
cmos vlsi design updated 4.3 years ago by teamques10 ★ 70k
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Find Drain current of $M_4$
cmos vlsi design updated 4.3 years ago by teamques10 ★ 70k
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Draw & explain floor plan for a possible mixed signal chip.
cmos vlsi design updated 4.3 years ago by teamques10 ★ 70k
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Find: Voltage gain $A_v$ / small signal $A_v$ for circuit
cmos vlsi design updated 4.3 years ago by teamques10 ★ 70k
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Explain Basic Current Mirror. Discuss Drawback and explain how cascode current Mirror overcomes it.
cmos vlsi design updated 4.3 years ago by teamques10 ★ 70k
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Calculate $V_{BE} $ of the following circuit.
cmos vlsi design updated 4.3 years ago by krithikkm200 • 10
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In the following fig. ,find drain current of $M_4$ if all the transistors are in saturation
cmos vlsi design updated 4.3 years ago by krithikkm200 • 10
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Calculate the small-signal voltage gain of the following circuit.
cmos vlsi design updated 4.3 years ago by krithikkm200 • 10
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Short note on SC Amplifier (Non-inv amp)
cmos vlsi design updated 4.3 years ago by teamques10 ★ 70k
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Explain PLL Topology
cmos vlsi design updated 4.3 years ago by teamques10 ★ 70k
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In following fig. sketch $V_x \ \&\ V_y$ as a function of $I_{Ref}$. If $I_{Ref}$ requires 0.5V to operate as a current source,what is its maximum value?
cmos vlsi design updated 4.3 years ago by krithikkm200 • 10
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