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What is Associative memory?
mumbai university computer organization and architecture updated 6 months ago by Saba Shaikh • 0
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State the various types of data transfer techniques. Explain DMA in detail. Or Explain the DMA based data transfer techniques for I/O devices?
mumbai university computer organization and architecture updated 6 months ago by Abhishek Tiwari ♦♦ 50
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What is bus arbitration? Explain any two techniques of bus arbitration. OR Explain Bus Contention and different method to resolve it
mumbai university computer organization and architecture updated 6 months ago by Abhishek Tiwari ♦♦ 50
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What are the types of pipeline hazards? or List and explain various data dependencies, data and branch hazards that occur in the computer system
mumbai university computer organization and architecture updated 6 months ago by Abhishek Tiwari ♦♦ 50
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Explain working of DMA and its different configuration.
mumbai university computer organization and architecture updated 9 months ago by Ankit Pandey • 70
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Explain different cache memory mapping techniques.
mumbai university computer organization and architecture updated 9 months ago by Ankit Pandey • 70
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Explain the hierarchical organization of computer memory.
mumbai university computer organization and architecture updated 9 months ago by Ankit Pandey • 70
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Explain Memory hierarchy. OR Explain in details Memory hierarchy with examples.
mumbai university computer organization and architecture updated 9 months ago by Ankit Pandey • 70
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Short note on flynns classification of parallel computer.
mumbai university computer organization and architecture updated 9 months ago by Ankit Pandey • 70
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What is DMA? Explain working of DMA
mumbai university computer organization and architecture updated 9 months ago by Abhishek Tiwari ♦♦ 50
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List and explain key characteristics of computer memory
mumbai university computer organization and architecture updated 9 months ago by Abhishek Tiwari ♦♦ 50
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Short Note on Pipeline Hazard OR What are the types of pipeline hazards?
mumbai university computer organization and architecture updated 9 months ago by Abhishek Tiwari ♦♦ 50
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Explain hardwired approach to the desing of a control unit.
mumbai university computer organization and architecture updated 9 months ago by Abhishek Tiwari ♦♦ 50
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What is virtual memory?
mumbai university computer organization and architecture updated 11 months ago by Sanket Shingote ♦♦ 270
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Compare Interrupt Driven I/O and DMA.
mumbai university computer organization and architecture updated 11 months ago by Abhishek Tiwari ♦♦ 50
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What are major requirements for an I/O module?
mumbai university computer organization and architecture updated 17 months ago by kaustubh • 10
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Explain with diagram functioning of Hardwired Control Unit.
mumbai university computer organization and architecture updated 20 months ago by umeshpatel00000 • 0
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Computer Organization and Architecture
computer organization and architecture updated 20 months ago by sufyanshah125.sss • 0
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Explain role of different registers like IR, PC, SP, AC, MAR and MDR used in $V_{nn}$ Neumann model.
mumbai university computer organization and architecture updated 23 months ago by Sakshi Naik • 0
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Question Paper: Computer Organization and Architecture : Question Paper Dec 2016 - Computer Engineering (Semester 4) | Mumbai University (MU)
question paper computer engineering (semester 4) computer organization and architecture mu updated 2.3 years ago by Team Ques10 ♦♦ 420
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Question Paper: Computer Organization and Architecture : Question Paper May 2016 - Information Technology (Semester 4) | Mumbai University (MU)
question paper computer organization and architecture information technology (semester 4) mu updated 2.3 years ago by Team Ques10 ♦♦ 420
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Question Paper: Computer Organization and Architecture : Question Paper Dec 2016 - Information Technology (Semester 4) | Mumbai University (MU)
question paper computer organization and architecture information technology (semester 4) mu updated 2.3 years ago by Team Ques10 ♦♦ 420
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Express (4.50)10 in the IEEE single and double precision standard of floating point representation.
mumbai university computer organization and architecture updated 2.6 years ago by Ravina Israni • 130
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Expain the design control unit wrt soft wired and hardwired
mumbai university computer organization and architecture updated 2.6 years ago by Ravina Israni • 130
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explain instruction cycle with interrupts execution with example
mumbai university computer organization and architecture updated 2.6 years ago by Ravina Israni • 130
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