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0
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1
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1.8k
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1
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Design a circuit with optimum utilization of PLA to implement following functions
digital circuits and design updated 3.8 years ago by pedsangini276 • 4.8k
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1
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21k
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1
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Write a VHDL code for 8:1 Multiplexer with active low enable input
digital circuits and design updated 3.8 years ago by pedsangini276 • 4.8k
0
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1
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2.0k
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1
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Write a VHDL code for full adder
digital circuits and design updated 3.8 years ago by pedsangini276 • 4.8k
0
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1
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2.6k
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1
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Short note on VHDL
digital circuits and design updated 3.8 years ago by pedsangini276 • 4.8k
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1
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35k
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1
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Write short note on: Stuck at '0' and stuck at '1' faults
digital circuits and design updated 3.8 years ago by pedsangini276 • 4.8k
2
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1
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6.5k
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1
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Write short note on: JTAG and BIST
digital circuits and design updated 3.8 years ago by pedsangini276 • 4.8k
0
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1
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3.5k
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1
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Write short note on: Automatic Test Pattern Generation (ATGP)
digital circuits and design updated 3.8 years ago by pedsangini276 • 4.8k
5
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2
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100k
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2
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Design Moore sequence detector to detect a sequence ----101-using DF/F
digital circuits and design updated 3.8 years ago by sagarkolekar ★ 11k
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1
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23k
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1
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Design a circuit with optimum utilization of PLA to implement the following functions F1= $\sum m(0,2,5,8,9,11), F2=\sum m(1,3,8,10,13,15), F3=\sum m(0,1,5,7,9,12,14).$
digital circuits and design updated 3.8 years ago by pedsangini276 • 4.8k
1
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1
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10k
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1
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Short note on multiplexers.
digital circuits and design updated 3.8 years ago by pedsangini276 • 4.8k
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1
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3.7k
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1
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Explain shift registers and its applications.
digital circuits and design updated 3.8 years ago by teamques10 ★ 70k
2
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1
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3.7k
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1
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Draw truth table and logical diagram of half adder
digital circuits and design updated 3.8 years ago by pedsangini276 • 4.8k
6
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1
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32k
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1
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Explain Fan-in, Fan-out, Power Dissipation and Noise Immunity with reference to Digital ICs
digital circuits and design updated 3.8 years ago by pedsangini276 • 4.8k
0
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1
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5.1k
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1
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Differentiate between Asynchronous and synchronous counters.
digital circuits and design updated 3.8 years ago by teamques10 ★ 70k
1
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1
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8.8k
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1
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**Implement following function using 8:1 MUX and logic gates.**
digital circuits and design updated 3.8 years ago by pedsangini276 • 4.8k
0
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1
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1.6k
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1
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Use K- map to reduce following function and then implement it by NOR gates.
digital circuits and design updated 3.8 years ago by pedsangini276 • 4.8k
2
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1
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35k
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1
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Design a Mealy sequence detector to detect ...0101...using D-flip flop and logic gates
digital circuits and design updated 3.8 years ago by pedsangini276 • 4.8k
1
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1
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1.9k
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1
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Simplify following logic functions and realize using NAND gates.
digital circuits and design updated 3.8 years ago by pedsangini276 • 4.8k
8
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1
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76k
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1
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Design MOD-12 asynchronous counter using T-flipflop.
digital circuits and design updated 3.8 years ago by teamques10 ★ 70k
0
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1
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3.8k
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1
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Write a VHDL code for full adder.
digital circuits and design updated 3.8 years ago by pedsangini276 • 4.8k
4
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1
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43k
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1
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Design 4-bit Johnson Counter using J=K flip-flop. Explain its operation using waveform.
digital circuits and design updated 3.8 years ago by teamques10 ★ 70k
-1
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1
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3.4k
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1
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Write a short note on fault model.
digital circuits and design updated 3.8 years ago by pedsangini276 • 4.8k
0
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1
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3.0k
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1
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Analyze the sequential-state-machine shown in figure. Obtain state diagram for the same.
digital circuits and design updated 3.8 years ago by pedsangini276 • 4.8k
0
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1
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4.7k
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1
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Design a Mealy type sequence detector to detect a serial input sequence of 101.
digital circuits and design updated 3.8 years ago by pedsangini276 • 4.8k
0
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1
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11k
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1
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Explain input and output block architecture for FPGA 4000 family.
digital circuits and design updated 3.9 years ago by teamques10 ★ 70k
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