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Digital Logic Design

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4.9k
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Short note on: Multi Vibrator
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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Convert SR Flip Flop to T Flip flop
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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Short note on: Decade Counter.
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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Short Note on: - State Table
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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Convert JK Flip flop to SR and D Flip Flop
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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Explain 3 bit Bidirectional shift register using JK Flip Flop. Draw the neat waveforms.
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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What is shift register? Explain 4-bit Bi-directional shift register?
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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Design 8-bit BCD.
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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Design a 2-bit digital comparator that accepts inputs A and B and gives three outputs G,E and L. i) Output G, when A>B ii) Output E, when A=B iii) Output L, when A<B
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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16k
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Design 1- bit comparator using logic Gate 5.
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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1
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Implement the following logic function using all 4:1 multiplexers with select inputs as 'B','C','D','E' only $F(A,B,C,D,E) = \sum m(0,1,2,3,6,8,9,10,13,15,17,20,24,30)$.
digital logic design updated 9.5 years ago by teamques10 ★ 70k
10
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150k
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Implement following Expression using 4:1 mux $F(A,B,C,D)=\sum m(0,1,2,4,6,9,12,14)$
digital logic design updated 9.5 years ago by teamques10 ★ 70k
5
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Explain with Example 4-bit BCD adder using IC- 7483.
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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Design a full adder using half adder and additional gates.
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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35k
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Design full adder using 3:8 decoder with active low outputs and NAND gates.
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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Implement the following expression using 8:1 mux $F(A,B,C,D)=\sum m(0,1,3,5,7,10,11,13,14,15)$
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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11k
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Implement the following using 8:1 mux: $F(A,B,C,D) = {\pi}M(1,3,5,9,11,12,13)$
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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Compare the performance of TTL ,CMOS and ECL Logic.
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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19k
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Define the following Parameters for CMOS family: i) Fan out ii) Fan in
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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1.8k
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Simplify the following function using k-map: $F(A,B,C,D) =\sum m(1,2,3,4,6,8,10,14,15).$
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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Given a logic Expression $A+\overline{B}\overline{C}+AB\overline{D}+ABCD \\ \text{(i) Express a standard SOP (ii) Draw k-map for the equation (iii) Minimize and realize using NAND Gate only}$
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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Simplify $Y=\overline{(A+\overline{A}B)(C+\overline{D})}$ .
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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Using the Quine Mc-Cluskey method determine minimized SOP form for: $F(A,B,C,D) = \sum m(1,2,3,6,7,10,12,14).$
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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1.8k
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Use Quine Mc-Cluskey method to simplify the logic function as given below. $F(A,B,C,D,E) = \sum m(0,1,8,10,11,12,20,21,30)+d(14,19)$ Realize the above using NAND gates .
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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1.9k
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Minimize the logic function using Quine-Mc-clusky method.$\\ \;$ $F(A B C D)=\sum m (1,3,7,9,10,11,13,15)$
digital logic design updated 9.5 years ago by teamques10 ★ 70k
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