Ask
Login
TAGGED IN

Digital Logic Design

Follow this tag to get notifications whenever a new post is added

ALL TAGS
0
votes
0
answers
184
views
0
answers
Up counter mod18 bascules jk
digital logic design updated 9 months ago by binitamayekar ★ 5.8k
0
votes
0
answers
558
views
0
answers
Ring counter and Working of Ring counter
digital logic design updated 10 months ago by pedsangini276 • 4.7k
0
votes
0
answers
155
views
0
answers
design a full adder using 3 to 8 line decoder.the decoder uses only the basic AND and NOT gates.
digital logic design updated 10 months ago by binitamayekar ★ 5.8k
0
votes
0
answers
289
views
0
answers
Design a counter with JK flip-flop capable of counting 3 to 5.
digital logic design updated 11 months ago by yashbeer ★ 10k
0
votes
0
answers
286
views
0
answers
Design a combinational logic circuit that implements F(A, B, C, D) of maximum terms = (0, 5, 9, 13) using 8-to-1 multiplexer block and A, C, B as control lines if an input X BCD number is even and has
digital logic design updated 11 months ago by binitamayekar ★ 5.8k
0
votes
0
answers
283
views
0
answers
VHDL code for Shift register using jk flip flop
digital logic design updated 12 months ago by yashbeer ★ 10k
0
votes
0
answers
1.1k
views
0
answers
Design a counter which counts the count from 3 to 12 using 1C74163 (10)
digital logic design updated 13 months ago by Krishna_Agrawal • 2.4k
0
votes
0
answers
395
views
0
answers
Design MOD using logic gates
digital logic design updated 13 months ago by Krishna_Agrawal • 2.4k
0
votes
0
answers
654
views
0
answers
Entity declaration in VHDL for NOR gate.
digital logic design updated 13 months ago by Krishna_Agrawal • 2.4k
0
votes
0
answers
899
views
0
answers
Design MOD-11 ripple counter using auto flip flop.
digital logic design updated 13 months ago by Krishna_Agrawal • 2.4k
0
votes
0
answers
1.2k
views
0
answers
Draw JKMS flip flop and explain its operation
digital logic design updated 13 months ago by Krishna_Agrawal • 2.4k
0
votes
0
answers
893
views
0
answers
Draw a neat circuit of master slave JK flip flop using logic gates. Write its truth table and explain its operation.
digital logic design updated 13 months ago by Krishna_Agrawal • 2.4k
0
votes
0
answers
972
views
0
answers
Implement the following boolean expression using 8:1 mux \[f\left(A,B,C,D\right)=\bar{A}\ \bar{B}\bar{C}+ABC+\bar{B}CD+\bar{A}CD\]
digital logic design updated 13 months ago by Krishna_Agrawal • 2.4k
0
votes
0
answers
304
views
0
answers
Using one's and two compliment methods perform (52)10-(18)10
digital logic design digital system design updated 13 months ago by pedsangini276 • 4.7k
0
votes
0
answers
490
views
0
answers
Write VHDL program for Ex-NOR gate?
digital logic design updated 13 months ago by sagarkolekar ★ 10k
0
votes
0
answers
467
views
0
answers
Weighted and non-weighted codes
digital logic design updated 13 months ago by pedsangini276 • 4.7k
0
votes
0
answers
266
views
0
answers
Implement the following Boolean function using single 4:1 MUX and few logic gates :- F(A,B,C,D)=?m(0,2,4,5,7,8,9,11,14)
digital logic design updated 13 months ago by Krishna_Agrawal • 2.4k
0
votes
0
answers
601
views
0
answers
Design a mod 6 ripple counter using T type flip-flop. Draw the circuit designed and output waeforms
digital logic design updated 13 months ago by Krishna_Agrawal • 2.4k
0
votes
0
answers
351
views
0
answers
For the following function implement the SOP and POS circuit F(A,B,C,D)=?m (2,3,5,7,12) + ?d(6,13,14,15)
digital logic design updated 13 months ago by Krishna_Agrawal • 2.4k
0
votes
0
answers
312
views
0
answers
How would you implement a16"I multiplexer using 2*1 multiplexers?
digital logic design updated 13 months ago by Krishna_Agrawal • 2.4k
2
votes
0
answers
364
views
0
answers
Design a full adder using 2 half adders. Explain its working
digital logic design updated 13 months ago by pedsangini276 • 4.7k
0
votes
0
answers
910
views
0
answers
Design a PROM which will convert BCD numbers into Gray code
digital logic design updated 15 months ago by yashbeer ★ 10k
1
vote
0
answers
533
views
0
answers
Question : Simplify the the equations using k-Map
digital logic design updated 4.5 years ago by doorabc2200 • 10
0
votes
0
answers
606
views
0
answers
Question: Implement the following expression using 8:1 mux and 16:1 mux
digital logic design updated 4.5 years ago by doorabc2200 • 10
<prev • 24 results • page 1 of 1 • next >