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Digital Logic Design

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14
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1
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194k
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1
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Design a mod 5 synchronous up counter using J-K flip flop
digital logic design updated 2.3 years ago by teamques10 ★ 64k
3
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1
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50k
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1
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What is multiplexer tree? Construct 32:1 multiplexer using 8:1 multiplexer only. Explain how the logic on particular data line is steered to the output in this design with example.
digital logic design updated 7.4 years ago by krrish • 350
1
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1
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28k
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1
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Obtain Even Parity hamming code for 1010. Prove that hamming code is an error detecting and correcting code.
digital logic design updated 2.2 years ago by yashbeer ★ 11k
4
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1
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12k
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1
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Describe a basic ecl Nor gate and explain its working in short with the suitable truth table and diagram?
digital logic design updated 2.0 years ago by binitamayekar ★ 6.4k
1
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1
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11k
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1
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Design a sequence generator for following sequence. Identify and check for lock out condition 0->3->5->6->0.
digital logic design updated 7.8 years ago by teamques10 ★ 64k
5
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1
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151k
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1
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Design mod-10 synchronous counter using JK Flip Flops.Check for the lock out condition.If so,how the lock-out condition can be avoided? Draw the neat state diagram and circuit diagram with Flip Flops.
digital logic design updated 2.3 years ago by teamques10 ★ 64k
10
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1
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92k
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1
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Design 4-bit binary to gray code conversion OR Design and implement 4 bit binary to gray code converter
digital logic design updated 2.5 years ago by teamques10 ★ 64k
2
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1
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13k
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1
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Short note on - Difference between CPLD and FPGA
digital logic design updated 7.8 years ago by teamques10 ★ 64k
1
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1
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20k
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1
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Explain 3 bit Bidirectional shift register using JK Flip Flop. Draw the neat waveforms.
digital logic design updated 7.8 years ago by teamques10 ★ 64k
2
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1
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4.2k
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1
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a) Represent $(29)_{10}$ into excess-3 code and Gray code.
digital logic design updated 4.6 years ago by teamques10 ★ 64k
4
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1
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72k
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1
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Implement the following expression using 8:1 mux $F(A,B,C,D)=\sum m(0,1,3,5,7,10,11,13,14,15)$
digital logic design updated 7.8 years ago by teamques10 ★ 64k
0
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1
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1.1k
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1
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Simplify this equation & realize using basic gates
digital logic design updated 3.4 years ago by teamques10 ★ 64k
0
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1
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1.1k
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1
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Draw the truth table for full adder and realize using 3:8 decoder
digital logic design updated 5.6 years ago by teamques10 ★ 64k
1
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1
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22k
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1
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Explain Multiplexer and Demultiplexer
digital logic design updated 3.4 years ago by teamques10 ★ 64k
0
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1
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926
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1
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Implement the following Boolean function using only one 8:1 Mux and few gates
digital logic design updated 3.4 years ago by teamques10 ★ 64k
0
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1
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861
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1
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Implement the following Boolean function using only one 4:1 Mux and few gates
digital logic design updated 3.4 years ago by teamques10 ★ 64k
1
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1
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9.2k
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1
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Write short notes on parity generator
digital logic design updated 5.6 years ago by teamques10 ★ 64k
0
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1
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13k
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1
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Universal gates. Implement EX-or gate using NAND gate.
digital logic design updated 3.4 years ago by teamques10 ★ 64k
0
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1
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864
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1
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Minimize the following Boolean expression using K-map
digital logic design updated 3.4 years ago by teamques10 ★ 64k
0
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1
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11k
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1
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Minimize the following four variable logic function using K-map and design by using basic gates
digital logic design updated 3.4 years ago by teamques10 ★ 64k
4
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1
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43k
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1
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Prove that NAND gate is universal gate
digital logic design updated 3.4 years ago by teamques10 ★ 64k
0
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1
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19k
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1
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What is Excess 3 codes? Why it is called as self complementary code.
digital logic design updated 3.4 years ago by teamques10 ★ 64k
0
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1
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770
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1
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Convert into Binary, Hexadecimal & Decimal
digital logic design updated 3.4 years ago by teamques10 ★ 64k
0
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1
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815
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1
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Convert into Binary & Decimal
digital logic design updated 3.4 years ago by teamques10 ★ 64k
0
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1
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45k
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1
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Short Note on Gray Code and Excess-3 Code.
digital logic design updated 17 months ago by sagarkolekar ★ 11k
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