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20
votes
1
answer
220k
views
1
answer
State and prove Demorgan's theorem
digital system design updated 5.8 years ago by abhishektiwari1 • 100
4
votes
1
answer
121k
views
1
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Explain the working of 3 bit asynchronous counter with proper timing diagram
digital system design updated 5.8 years ago by abhishektiwari1 • 100
5
votes
1
answer
98k
views
1
answer
Design 3 bit Binary to Gray code converter
digital system design updated 5.8 years ago by abhishektiwari1 • 100
7
votes
1
answer
67k
views
1
answer
Prove that NAND and NOR gates are Universal gates
digital system design updated 5.8 years ago by abhishektiwari1 • 100
3
votes
1
answer
40k
views
1
answer
Design a VHDL Code for 4 bit full adder.
digital system design updated 3.5 years ago by pedsangini276 • 4.8k
1
vote
1
answer
39k
views
1
answer
Write Short note on ROM & RAM architecture.
digital system design updated 3.5 years ago by pedsangini276 • 4.8k
2
votes
1
answer
33k
views
1
answer
Explain Full Adder circuit using PLA having three inputs, 8 product terms and two outputs.
digital system design updated 5.8 years ago by abhishektiwari1 • 100
2
votes
1
answer
31k
views
1
answer
Compare Between Concurrent & Sequential Statements
digital system design updated 3.5 years ago by pedsangini276 • 4.8k
2
votes
2
answers
26k
views
2
answers
Differentiate between Mealy Machine and Moore Machine.
digital system design updated 3.3 years ago by yashbeer ★ 11k
0
votes
1
answer
26k
views
1
answer
Design a 2 bit comparator and implement using logic gates
digital system design updated 5.8 years ago by abhishektiwari1 • 100
2
votes
1
answer
21k
views
1
answer
VHDL Code for Full Subtractor
digital system design updated 5.8 years ago by abhishektiwari1 • 100
0
votes
1
answer
20k
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1
answer
Compare TTL and CMOS logic families
digital system design updated 5.8 years ago by abhishektiwari1 • 100
3
votes
1
answer
17k
views
1
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Draw and explain 3 bit asynchronous binary counter using positive edge triggered JK flip flop. Draw the waveforms.
digital system design updated 5.8 years ago by abhishektiwari1 • 100
1
vote
1
answer
17k
views
1
answer
Write a Short Note on Modeling Styles of VHDL.
digital system design updated 3.2 years ago by teamques10 ★ 70k
0
votes
1
answer
17k
views
1
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Design a VHDL Code for T Flip-Flop.
digital system design updated 3.5 years ago by pedsangini276 • 4.8k
1
vote
1
answer
14k
views
1
answer
Convert JK Flip Flop to T Flip Flop
digital system design updated 5.8 years ago by abhishektiwari1 • 100
1
vote
1
answer
14k
views
1
answer
Write VHDL code for 3 bit up counter
digital system design updated 5.8 years ago by abhishektiwari1 • 100
0
votes
1
answer
14k
views
1
answer
Design a VHDL Code for 4 Bit Ripple Carry Adder.
digital system design updated 3.5 years ago by pedsangini276 • 4.8k
0
votes
1
answer
14k
views
1
answer
Design a mealy sequence detector to detect 1010 using D flip-flops & Logic Gates.
digital system design updated 3.5 years ago by pedsangini276 • 4.8k
0
votes
1
answer
14k
views
1
answer
Design a VHDL Code for Multiplexer & Demultiplexer.
digital system design updated 3.5 years ago by pedsangini276 • 4.8k
0
votes
1
answer
13k
views
1
answer
Write VHDL code for Fibonacci Series Generator.
digital system design updated 5.8 years ago by abhishektiwari1 • 100
1
vote
1
answer
12k
views
1
answer
Implement the following Boolean function with 8: multiplexer F(A,B,C,D)=?m(0,3,5,6,8,9,10,12,14).
digital system design updated 4.1 years ago by teamques10 ★ 70k
0
votes
1
answer
12k
views
1
answer
Write a VHDL Code for JK Flip-Flop.
digital system design updated 3.5 years ago by sagarkolekar ★ 11k
0
votes
1
answer
12k
views
1
answer
Write Short note on PLA, PAL architecture.
digital system design updated 3.5 years ago by pedsangini276 • 4.8k
1
vote
1
answer
12k
views
1
answer
Features of VHDL
digital system design updated 3.3 years ago by DevarenjiniP • 3.2k
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