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1.3k

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Draw CLA adder using i) static CMOS ii) Dynamic CMOS logic iii) Pseudo NMOS logic

vlsi design updated 4.2 years ago by teamques10 ★ 70k

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752

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Design $4 \ast 4$ barrel shifter

vlsi design updated 4.2 years ago by teamques10 ★ 70k

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768

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Explain interconnect scaling with its length, width, thickness, and capacitance

vlsi design updated 4.2 years ago by teamques10 ★ 70k

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994

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Explain how ESD affect MOS. Give and explain input protection circuits

vlsi design updated 4.2 years ago by teamques10 ★ 70k

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1.3k

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Explain low power design considerations

vlsi design updated 4.2 years ago by teamques10 ★ 70k

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1.2k

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Explain resistance and capacitance estimation

vlsi design updated 4.2 years ago by teamques10 ★ 70k

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1.9k

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Compare Ripple carry adder and carry lookahead adder

vlsi design updated 4.2 years ago by teamques10 ★ 70k

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944

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Explain concept of carry look ahead adder with equation & how does it achieve better speed as compared to ripple carry adder

vlsi design updated 4.2 years ago by phenjoisilab • 0

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1.1k

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Explain drawback of RCA .Explain 4 bit CLA adder with its carry equation logical network using Dynamic CMOS logic

vlsi design updated 4.2 years ago by phenjoisilab • 0

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1.1k

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Implement $4 \ast 4$ barrel shifter using transmission gate >Explain various operation using the same

vlsi design updated 4.2 years ago by phenjoisilab • 0

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813

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Implement following function using CMOS F=AB+AC+AB

vlsi design updated 4.2 years ago by phenjoisilab • 0

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829

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Draw JK FF using CMOS & explain its working

vlsi design updated 4.2 years ago by phenjoisilab • 0

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904

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Draw CLA carry chain using dynamic CMOS logic

vlsi design updated 4.2 years ago by phenjoisilab • 0

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808

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design decoder circuit for ROM array

vlsi design updated 4.2 years ago by phenjoisilab • 0

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970

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Give read & write stability criterion for 6 T RAM if the pullup transistors are replaced by resistors

vlsi design updated 4.2 years ago by phenjoisilab • 0

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738

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Draw CMOS implementation of D FF

vlsi design updated 4.2 years ago by phenjoisilab • 0

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748

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explain concept of Charge Sharing & Charge Lekage

vlsi design updated 4.2 years ago by phenjoisilab • 0

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1.9k

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Explain effect on drain current due to channel length modulation & velocity saturation

vlsi design updated 4.2 years ago by phenjoisilab • 0

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1.0k

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Consider CMOS circuit with following parameters $v_{DD}=3.3v,v_{TOn}=0.6v,v_{TO},p=-0.7v,\mu_nC_{ox}=60 \mu A/v^2, \mu_pC_{ox}=20 \mu A/v^2, (W/L)n=8,(W/L)p=12$Calculate noise margins of the circuit

vlsi design updated 4.2 years ago by phenjoisilab • 0

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1.8k

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What are the drawbacks of dynamic CMOS logic show the modification in dynamic CMOS logic to overcome its drawback

vlsi design updated 4.2 years ago by phenjoisilab • 0

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3.0k

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For equal rise time & fall delay time assume $\mu_n=2 \mu_p$ .Draw an inverter equivalent circuit of 3 Input NAND gate & 2 input XOR

vlsi design updated 4.2 years ago by phenjoisilab • 0

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1.1k

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Define Scaling .Explain various types of scaling

vlsi design updated 4.2 years ago by phenjoisilab • 0

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1.8k

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Compare Constant voltage & constant field scaling with their merits & demerits

vlsi design updated 4.2 years ago by phenjoisilab • 0

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965

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Explain significance of sacling in VLSI circuits

vlsi design updated 4.2 years ago by phenjoisilab • 0