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Digital Logic Design

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(Duplicate) Explain Full Adder circuit using PLA having 4 inputs, 8 product terms and 4 outputs
digital logic design updated 3.8 years ago by abhi022mahajan • 0
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Obtain Even Parity hamming code for 1010. Prove that hamming code is an error detecting and correcting code.
digital logic design updated 3.9 years ago by yashbeer ★ 11k
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Write a VHDL code for full adder.
digital logic design updated 3.9 years ago by yashbeer ★ 11k
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Write VHDL code for 3-bit up counter
digital logic design updated 3.9 years ago by yashbeer ★ 11k
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Write the VHDL code for 2-bit up-down counter with positive edge triggered clock.
digital logic design updated 3.9 years ago by yashbeer ★ 11k
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Short note on: VHDL
digital logic design updated 3.9 years ago by teamques10 ★ 70k
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COMPARISON OF ANALOG and DIGITAL SIGNAL
digital logic design updated 3.9 years ago by teamques10 ★ 70k
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Explain the transfer characteristics of TTL NAND gate and hence define Fan-in and Fan-out.
digital logic design updated 3.9 years ago by teamques10 ★ 70k
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4-bit Magnitude Comparator
digital logic design updated 3.9 years ago by phenjoisilab • 0
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Arithmetic and logical unit.
digital logic design updated 3.9 years ago by phenjoisilab • 0
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Draw truth table of full sub tractor and realize it using 3:8 decoder.
digital logic design updated 3.9 years ago by phenjoisilab • 0
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Design and implement one digit BCD tables.
digital logic design updated 3.9 years ago by phenjoisilab • 0
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Explain ASCII Code
digital logic design updated 3.9 years ago by phenjoisilab • 0
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Explain De Morgan's laws
digital logic design updated 3.9 years ago by phenjoisilab • 0
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Simplify using $\theta$ using Mc.clusky method.
digital logic design updated 3.9 years ago by phenjoisilab • 0
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4-bit universal shift register.
digital logic design updated 3.9 years ago by abhi022mahajan • 0
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Advantages and Disadvantages of using Multiplexer.
digital logic design updated 3.9 years ago by phenjoisilab • 0
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Universal Shift Register.
digital logic design updated 3.9 years ago by phenjoisilab • 0
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Implementation using 8 : 1 MUX
digital logic design updated 3.9 years ago by phenjoisilab • 0
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Explain Demorgan's law
digital logic design updated 3.9 years ago by phenjoisilab • 0
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State Diagram, State table, State assignment, Excitation table and maps
digital logic design updated 3.9 years ago by phenjoisilab • 0
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Eliminate redundant states and draw reduced state diagram (10)
digital logic design updated 3.9 years ago by phenjoisilab • 0
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Standard SOP form
digital logic design updated 3.9 years ago by phenjoisilab • 0
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858
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Explain in detail truth table
digital logic design updated 3.9 years ago by phenjoisilab • 0
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BCD and Ex-3 codes
digital logic design updated 3.9 years ago by phenjoisilab • 0
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