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Digital Logic Design

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2
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Design a full adder using 2 half adders. Explain its working
digital logic design updated 3.3 years ago by pedsangini276 • 4.8k
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2.2k
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Draw JKMS flip flop and explain its operation
digital logic design updated 3.2 years ago by Krishna_Agrawal • 2.7k
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456
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Up counter mod18 bascules jk
digital logic design updated 2.9 years ago by binitamayekar ★ 6.7k
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435
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design a full adder using 3 to 8 line decoder.the decoder uses only the basic AND and NOT gates.
digital logic design updated 3.0 years ago by binitamayekar ★ 6.7k
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656
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Design a counter with JK flip-flop capable of counting 3 to 5.
digital logic design updated 3.1 years ago by yashbeer ★ 11k
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677
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VHDL code for Shift register using jk flip flop
digital logic design updated 3.2 years ago by yashbeer ★ 11k
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1.9k
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Using one's and two compliment methods perform (52)10-(18)10
digital logic design digital system design updated 3.2 years ago by pedsangini276 • 4.8k
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1.6k
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Draw a neat circuit of master slave JK flip flop using logic gates. Write its truth table and explain its operation.
digital logic design updated 3.2 years ago by Krishna_Agrawal • 2.7k
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790
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Weighted and non-weighted codes
digital logic design updated 3.2 years ago by pedsangini276 • 4.8k
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1.8k
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Design a PROM which will convert BCD numbers into Gray code
digital logic design updated 3.4 years ago by yashbeer ★ 11k
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1.8k
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Implement the following boolean expression using 8:1 mux \[f\left(A,B,C,D\right)=\bar{A}\ \bar{B}\bar{C}+ABC+\bar{B}CD+\bar{A}CD\]
digital logic design updated 3.2 years ago by Krishna_Agrawal • 2.7k
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513
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Implement the following Boolean function using single 4:1 MUX and few logic gates :- F(A,B,C,D)=?m(0,2,4,5,7,8,9,11,14)
digital logic design updated 3.2 years ago by Krishna_Agrawal • 2.7k
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1.7k
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Design a mod 6 ripple counter using T type flip-flop. Draw the circuit designed and output waeforms
digital logic design updated 3.2 years ago by Krishna_Agrawal • 2.7k
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868
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For the following function implement the SOP and POS circuit F(A,B,C,D)=?m (2,3,5,7,12) + ?d(6,13,14,15)
digital logic design updated 3.2 years ago by Krishna_Agrawal • 2.7k
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573
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How would you implement a16"I multiplexer using 2*1 multiplexers?
digital logic design updated 3.3 years ago by Krishna_Agrawal • 2.7k
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774
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Question : Simplify the the equations using k-Map
digital logic design updated 6.7 years ago by doorabc2200 • 10
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874
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Question: Implement the following expression using 8:1 mux and 16:1 mux
digital logic design updated 6.7 years ago by doorabc2200 • 10
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1.4k
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Design MOD-11 ripple counter using auto flip flop.
digital logic design updated 3.2 years ago by Krishna_Agrawal • 2.7k
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1.1k
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Entity declaration in VHDL for NOR gate.
digital logic design updated 3.2 years ago by Krishna_Agrawal • 2.7k
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1.6k
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Design a counter which counts the count from 3 to 12 using 1C74163 (10)
digital logic design updated 3.2 years ago by Krishna_Agrawal • 2.7k
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694
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Design MOD using logic gates
digital logic design updated 3.2 years ago by Krishna_Agrawal • 2.7k
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589
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Design a combinational logic circuit that implements F(A, B, C, D) of maximum terms = (0, 5, 9, 13) using 8-to-1 multiplexer block and A, C, B as control lines if an input X BCD number is even and has
digital logic design updated 3.1 years ago by binitamayekar ★ 6.7k
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845
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Write VHDL program for Ex-NOR gate?
digital logic design updated 3.2 years ago by sagarkolekar ★ 11k
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952
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Ring counter and Working of Ring counter
digital logic design updated 3.0 years ago by pedsangini276 • 4.8k
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